The invention relates to topography for integrated circuit microprocessor chips.
The size of an integrated circuit, i.e., the "chip size" is an important factor in the ultimate cost of the integrated circuit to the final user. Another important cost is the engineering and design cost. The larger the number of units of the integrated circuit which are manufactured per wafer, the smaller are the engineering and design costs per unit. However, the chip size becomes an increasingly dominate factor in the ultimate product cost as the manufacturing volume of the product increases. For state of the art CMOS (complementary metal-oxide-semiconductor) and MOS (metal-oxide-semiconductor) large scale integrated (LSI) devices, very large numbers of MOSFET's (metal-oxide-semiconductor field effect transistors) are fabricated on a single monolithic silicon "chip", which is frequently less than 200 mils square. Thousands of conductive lines, some composed of polycrystaline silicon, others composed of aluminum, and others composed of diffused regions within the silicon, interconnct the electrodes of the various MOSFETs. Minimum line widths and spacings between the respective lines and the MOSFETs must be maintained to avoid short circuits and parasitic effects despite slight variations in the manufacturing process due to presence of minute, even submicron, particulates that are invariably present in the semiconductor processing facility. Yet the length of the interconnecting lines and their associated capacitanaces must be minimized, not only to reduce chip size, but also to achieve maximum circuit operating speeds. A wide variety of trade-offs, including the necessity to minimize chip size, obtain a suitable chip aspect ratio (which enhances integrated circuit chip yield and wire bonding yield), increase circuit operating speed, reduce power consumption, and achieve acceptable reliability are all involved in obtaining an optimum "layout" or topography of the MOSFETs and the interconnection pattern therebetween in order to obtain an MOSLSI circuit which is both economical and has acceptable operating characteristics. Often, the technical and commercial success of an electronic product utilizing MOSLSI technology may hinge on the ability of the chip designer to achieve an optimum chip topography.
A very high level of creative interaction between the circuit designer and the chip designer or layout draftsman is required to achieve a chip topography or layout which enables the integrated circuit to have acceptable operating speed and power dissipation and yet is sufficiently small to be economically feasible. Months of such interaction resulting in numerous trial layout designs and redesigns and circuit design revisions may be required to arrive at an optimum topography for a single MOSLSI chip. Although the computer aided design (CAD) approach in the past has been attempted in order to generate optimum MOSLSI topography designs, this approach has been only moderately successful, and only to the extent that the CAD approach usually provides a rapid chip topography design. However, such a topography design usually results in less than optimum, or even mediocre performance and usually results in an unnecessarily large semiconductor chip. It is established in the integrated circuit industry that CAD approaches to generating MOSLSI chip layouts do not yet achieve the topography design optimization which can be accomplished by human ingenuity applied to the task.
Some of the numerous design constraints faced by the MOSLSI chip designer include specifications for minimum widths and spacings of diffused regions in the silicon, the minimum size required for contact openings in the insulating field oxide, the spacings required between the edges of contact openings to the edges of diffused regions, minimum widths and spacings of polycrystaline silicon conductors, the fact that such polycrystaline silicon conductors cannot "cross over" diffused regions in most silicon gate processes, the minimum widths of and spacings between the aluminum metalization conductors, and the constraint that conductors on the same layer of insulating oxide cannot cross over like conductors. The high amount of capacitance associated with diffused regions and the resistance of both diffused regions and polycrystaline silicon conductors must be carefully considered by the circuit designer and the chip designer in arriving at an optimum chip topography. For many types of logic circuits, such as the microprocessor of the present invention, an extremely large number of conductive lines between sections of logic circuitry are required. The practically infinite number of possibilities for routing the various conductors and placement of the various MOSFETs taxes the skill and ingenuity of even the most resourceful chip designers and circuit designers, and is beyond the capability of the most sophisticated computer programs yet available. Other constraints faced by the chip designer and circuit designer involve the need to minimize cross-coupling and parasitic effects which occur between various conductive lines and conductive regions. Such effects may degrade voltages on various conductors, leading to inoperative circuitry or low reliability operation under certain operating conditions.
In approximately 1976, an NMOS (N channel MOS) integrated circuit microprocessor referred to as the 6502 microprocessor was introduced to the market. Earlier, Motorola had introduced an NMOS integrated circuit microprocessor known as the 6800 microprocessor. The 6800 and the 6502 are similar in certain respects. U.S. Pat. No. 3,987,418 discloses the topography of the 6800. Some of the most basic features of the 6800 microprocessor topography were used in the 6502, including placement of the instruction decoder at the top of the chip as illustrated in FIG. 6 of that patent, placement of the instruction register to the left of the instruction decoder, placement of the address output buffers along the bottom and lower left hand sides of the chip, placement of the data bus buffers along the lower right hand side of the chip, and placement of the register sections and the arithmetic logic unit generally to the left of the data bus buffers in the lower portion of the chip. Nevertheless, many subtle changes in circuit design, logic design, and topography design were provided in the 6502 microprocessor. Both processors have been widely used. However, both microprocessors dissipate a high amount of operating power, and neither now can be considered to be state-of-the-art devices.
The CMOS (complementary MOS) integrated circuit technology has been known for many years. The popularity of this technology has gradually grown, due to the very low static or DC power dissipation of conventional CMOS circuits. Also, the operating speed of CMOS circuitry is usually somewhat higher than that of NMOS integrated circuitry. However, the manufacturing costs of CMOS integrated circuits are higher than for NMOS integrated circuits due to the greater complexity of this semiconductor manufacturing process. Furthermore, due to the need to provide so-called "P-tubs" in which the N channel MOSFETs must be diffused (whereas the P channel devices can be diffused directly into the substrate) CMOS integrated circuits generally have required larger chips than functionally equivalent NMOS circuits.
Nevertheless, it occurred to me that if a CMOS microprocessor pin-compatible with and software compatible with the "ancient" 6502 could be designed with greatly reduced power consumption, greatly increased circuit operating speeds, and with certain functional improvements, it might be readily received by the marketplace.
Therefore, it is an object of this invention to provide an improved CMOS microprocessor compatible with the 6502, having certain improved functional features, and having a topography which results in a much faster, lower power dissipation microprocessor chip that can compete very favorably in the marketplace with the NMOS 6502 microprocessor.